Semiconductor device models, such as transistor models, are vital in achieving reliable performance from circuit designs using semiconductor devices. Moreover, semiconductor device models can significantly increase the efficiency of the circuit design process.
Compact transistor models such as BSIM4 (Berkeley Short-channel IGFET Model 4) are simplified physical models typically employed in circuit simulators, for example SPICE (Simulation Program with Integrated Circuit Emphasis) to model the behavior of semiconductor devices such as CMOS (Complementary Metal-Oxide-Semiconductor) field effect transistors in integrated circuits. The set of parameters that specify the behavior of a particular semiconductor device are stored in a data structure called a model card, which is used as an input to a SPICE simulation process.
In contemporary semiconductor technologies, notionally identical devices may in actuality have radical variations in performance due to intrinsic parameter fluctuations that are caused by physical phenomena such as random discrete dopants (RDD), line edge roughness (LER) and metal gate granularity (MGG).
One method to incorporate such variations into compact models is to take a “uniform” model that is fitted to the “average” performance of the device and re-extract a subset of the model parameters to adjust the performance to match that of individual instances. This yields a statistical distribution for each model parameter that is re-extracted. Such distributions may also be correlated with each other to a certain degree.
Monte Carlo circuit simulations can then employ such models to estimate the statistical distributions of key performance metrics of CMOS standard cells. The traditional approach to this entails substituting one of the above extracted model cards in place of each transistor in the circuit. This necessarily imposes limits on the scenarios that can be analyzed in that the models are only valid for e.g. a specific process geometry. Additional limitations are imposed by the fact that one model card corresponds to one transistor instance, for which target data must be obtained either from measurement or from TCAD (Technology Computer Aided Design) simulation. As the problem space scales up, this becomes a significant consideration.
In addition to the static intrinsic variability sources such as random discrete dopant RDD and line edge roughness LER, there are time-dependent effects that are of concern in contemporary deep submicron technologies. This includes negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI), which are degradation mechanisms by which performance is reduced when the transistor is subject to electrical and thermal stress. NBTI and PBTI have both recoverable and permanent effects on performance. The recoverable portion of the performance reduction is removed once the external stress is removed, however the permanent component remains, and is of great concern when considering product lifetime and mean time to failure. NBTI and PBTI are of particular concern in high-k metal gate technologies.
Previous approaches to modeling reliability as a statistical phenomenon have tended to treat it as distinct from the static variations arising from RDD, LER and metal gate granularity MGG. However it is known that bias temperature instability (BTI) can have strong interactions with RDD, producing unusually large performance shifts. The likelihood of such shifts increases as the cumulative stress increases, i.e. the circuit ages. It is therefore desirable for this to be accurately included in compact models used for evaluating yield—particularly for circuits in the late stages of degradation.
A known approach for including the effects of BTI in compact models is to employ the same strategy as for static variability. That is, to re-extract a subset of the model parameters to capture the changes in performance. This approach can also be applied to capture the permanent component of circuit ageing. This leads to model parameter distributions that effectively evolve over time in a certain fashion.
However, it is a problem that known approaches do not accurately model time dependent degradation and reliability of semiconductor devices.